(a) Field of the Invention
The invention relates to a charge pump circuit for use in a phase locked loop.
(b) Description of the Related Art
As is well known in the art, a phase locked loop (PLL) comprises a loop filter including a capacitor therein, a voltage controlled oscillator (VCO), a frequency divider, a phase/frequency comparator, and a charge pump circuit cascaded to form a feed-back loop. The loop filter functions as a low pass filter (LPF), and produces a control voltage across the capacitor terminals, the control voltage controlling the VCO to generate an output signal of the PLL having a frequency in response to the control voltage. The frequency divider divides the frequency of the output signal in accordance with a specified factor, thus producing a divided-frequency signal. The phase/frequency comparator, or phase/frequency detector, compares the divided-frequency signal against an input reference frequency signal, and detects a phase/frequency difference between the reference frequency signal and the divided-frequency signal, so as to generate UP/DOWN signals based on the phase/frequency difference between both the signals. In response to UP signal, the charge pump circuit provides electric charge to the loop filter, thereby charging the capacitor therein. Also, in response to DOWN signal, the charge pump circuit drains electric charge from the loop filter, thereby discharging the capacitor therein.
FIG. 1 shows a charge pump circuit 601 for use in the PLL as a first conventional technique. The charge pump circuit 601 has a first input terminal 61 for receiving UP signal, a second input terminal 62 for receiving DOWN (DN) signal, an output terminal 63 through which electric charge is provided to or drained from the loop filter by flowing a control current I.sub.P ', a power supply terminal 64 connected to line voltage +Vdd, and a ground terminal 65 for grounding. UP signal is active at a low level thereof while DN signal is active at a high level thereof.
The charge pump circuit 601 comprises therein a first (constant) current source 71, a first P-channel MOSFET 72, a second (constant) current source 73, and a first N-channel MOSFET 74. The first current source 71 is connected to the power supply terminal 64 for supplying a first constant current I.sub.P1. The first P-channel MOSFET 72 has a source connected to the first current source 71, a gate for receiving UP signal and a drain connected to the output terminal 63 of the charge pump circuit. The first P-channel MOSFET 72 supplies first constant current I.sub.P1 to the output terminal 63 in response to UP signal. The second current source 73 is connected to the ground terminal 65 for supplying a second constant current I.sub.P2. The first N-channel MOSFET 74 is connected between the second current source 73 and the output terminal 63 for draining the second constant current I.sub.P2 from the output terminal put 63 in response to DN signal.
During the time period the first P-channel MOSFET 72 or first N-channel MOSFET 74 is on, the output terminal 63 is charged or discharged by the first constant current I.sub.P1 or I.sub.P2, thus controlling the current signal IP' for the loop filter. In other words, the charge pump circuit 601 delivers or drains electric charge, depending on the pulse width of UP signal or DN signal, to or from the loop filter. Thus, the output frequency of the VCO varies in accordance with the control voltage delivered through the loop filter.
It will be noted that each of the MOSFETs 72 and 73 has a junction capacitance, and accordingly, first and second parasitic capacitances C1 and C2 are formed from a first node N1 between the first current source 71 and the first P-channel MOSFET 72 to the ground, and from a second node N2 between the second current source 73 and the first N-channel MOSFET 74 to the ground, respectively.
Referring additionally to FIG. 2 for showing the signal waveforms in the charge pump circuit, the operation of the charge pump circuit 601 of FIG. 1 will be described. When UP signal falls to be active, the first P-channel MOSFET 72 is turned on to supply a current signal I.sub.P ' which includes a first constant current Ip1 and a spike current I.sub.OC1 superposed to the first constant current I.sub.P1 at the leading edge thereof, the spike current I.sub.OC1 being supplied from the first parasitic capacitance C1.
Similarly, when DN signal rises to be active, the first N-channel MOSFET 74 is turned on to supply a current signal I.sub.P ' which includes the second constant current I.sub.P2 and a spike current I.sub.OC2 superposed to the second constant current I.sub.P2 at the leading edge thereof, the spike current I.sub.OC2 being supplied from the second parasitic capacitance C2.
The spike currents I.sub.OC1 and I.sub.OC2 have respective magnitudes independently of the pulse width of UP or DN signal. Accordingly, after the PLL is locked in phase with the reference signal, wherein the magnitude of a phase/frequency difference .DELTA.f0 supplied from the phase/frequency comparator is reduced to a minimum, a significant variation occurs in the control voltage for the VCO, whereby the output signal of the VCO includes a jitter, such as shown in FIG. 3.
FIG. 4 shows a second conventional charge pump circuit, wherein like constituent elements are designated by like reference numerals in FIGS. 1 and 2 and other drawings. The charge pump circuit 602 is similar to the charge pump circuit 601 of FIG. 1 except that the first and second constant current sources 71 and 72 are connected between the output terminal 63 and the drains of the P-channel and N-channel MOSFETs 72 and 74, respectively. In this configuration, parasitic capacitances C1 and C2 are associated with the drains of the P-channel and N-channel MOSFETs 72 and 74, respectively.
Referring additionally to FIG. 5 showing, similarly to FIG. 3, signal waveforms in the charge pump circuit 602 of FIG. 4, the output current signal I.sub.P " to the loop filter includes the first constant current I.sub.P1 and a spike current I.sub.OC1 ' at the trailing edge thereof when UP signal is active, and includes the second constant current I.sub.P2 and a spike current I.sub.OC2 ' at the trailing edge thereof when DN signal is active, both the spike currents I.sub.OC1 ' and I.sub.OC2 ' being supplied from the parasitic capacitnaces C1 and C2, respectively. The output of the VCO receiving the current signal I.sub.P " includes a jitter similarly to the case of the first conventional charge pump circuit 601.
In order to solve the problem jitter as described above, there has been a technique proposed in which the influence of the parasitic capacitance is eliminated by maintaining a junction associated with the parasitic capacitance at the same potential as the output terminal 63. The technique is disclosed by Ian A. Young et al in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.27, NO.11, NOVEMBER 1992, entitled "A PLL Clock Generator with 5 to 110 MHZ of Lock Range for Microprocessors" (third conventional technique).
FIG. 6 shows a charge pump circuit generally designated at 603, which is substantially identical to the disclosure of the article as mentioned above. The charge pump circuit 603 comprises a main circuit block 70 similar to the charge pump circuit 601 of FIG. 1 and an additional, potential-equalizing block 90.
The potential-equalizing block 90 comprises a first and a second inverters 91 and 92, a second P-channel MOSFET 93, a second N-channel MOSFET 94, and a unity gain amplifier, voltage follower 95, implemented by an operational amplifier 951.
In the voltage follower 95, the operational amplifier 951 has a non-inverting input connected to the output terminal 63 of the charge pump circuit 603, and an inverting input connected to the output 951a of the operational amplifier 951, which constitutes the output 95a of the voltage follower 95. The first inverter 91 inverts UP signal to supply an inverted UP (XUP) signal, and the second inverter 92 inverts DN signal to supply an inverted DN (XDN) signal.
The second P-channel MOSFET 93 includes a source connected to the node N1 associated with the first parasitic capacitance C1, a drain connected to the output 95a of the voltage follower 95, and a gate for receiving XUP signal. The second N-channel MOSFET 94 includes a source connected to the node N2 associated with the second parasitic capacitance C2, a drain connected to the output 95a of the voltage follower 95, and a gate for receiving XDN signal.
With the described arrangement, during a time interval when the first P-channel MOSFET 72 is off, the node N1 is maintained at the potential Vc of the output terminal 63, which is the control voltage supplied to the loop filter. Similarly, during a time interval when the first N-channel MOSFET 74 is off, the node N2 is maintained at the control voltage Vc of the output terminal 63. In this manner, the influence of the charge supplied from the parasitic capacitances C1 and C2 can be eliminated.
Another charge pump circuit similar to the charge pump circuit 603 of FIG. 6, except that the MOSFETs 93 and 94 shown in FIG. 6 are of normally off type, is described in Patent Publication NO. JP-A-1989-177,867 (fourth conventional technique).
Another charge pump circuit is also known for reducing the influence of a parasitic capacitance. For example, Patent Publication No. JP-A-1991-126,257 describes a CMOS charge pump circuit in which a P-channel MOSFET in the first current source and the first P-channel MOSFET such as shown in FIG. 1 are formed in a common diffused region, and an N-channel transistor in the second current source and the first N-channel MOSFET such as shown in FIG. 1 are formed in another common diffused region (fifth conventional technique). Patent Publication NO. JP-A-1990-63,219 describes another charge pump circuit which additionally includes a P-channel MOSFET which serves for maintaining a potential at the node between the output terminal and the drain of the P-channel MOSFET in the first current source at a voltage in the vicinity of a threshold voltage, and an N-channel MOS transistor which serves for maintaining a potential at the node between the output terminal and the drain of the N-channel MOSFET in the second current source at a voltage in the vicinity of the threshold voltage (sixth conventional technique).
Those approaches indicated by the third and fourth conventional techniques has disadvantages of a high fabrication cost and an increased layout area because of an increased number of elements required. In addition, the approaches have a draw back of a slow operational speed because the operational amplifier has a time delay as large as on the order of 10 nanoseconds. Further, the operational amplifier involves a higher power dissipation.
The approach suggested by the fifth conventional technique is to reduce the parasitic capacitance as much as possible, and thus it is unable to eliminate the influence of the parasitic capacitance. The approach suggested by the sixth conventional technique is to maintain a constant current from the parasitic capacitance to the output terminal, but also fails to eliminate the influence of the parasitic capacitance, as is the case of the fifth conventional technique.